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general description the MAX9507 amplifies and filters standard-definition video signals and only consumes 5.8mw quiescent power and 11.7mw average power. the MAX9507 leverages maxim? directdrive technology to gener- ate a clean, internal negative supply. combining the internal negative power supply with the external posi- tive 1.8v supply, the MAX9507 is able to drive a 2v p-p video signal into a 150 load. the MAX9507 provides an i 2 c interface for easy configu- ration and access to the load status. the MAX9507 can detect, report, and act upon the change of a video load. this feature helps reduce overall power consumption by allowing the system to turn on the video encoder and dri- ver only when a video load is connected to the MAX9507. with a high power-supply rejection ratio (47db at 100khz), the MAX9507 can be powered directly from a 1.8v digital supply. the two integrated single-pole/sin- gle-throw (spst) analog switches are ideal for routing audio, video, or digital signals. the input of the MAX9507 can be directly connected to the output of a video dac. the MAX9507 also features a transparent input sync-tip clamp, allowing ac-cou- pling of input signals with different dc biases. the MAX9507 has an internal fixed gain of 8. the input full-scale video signal is nominally 0.25v p-p , and the output full-scale video signal is nominally 2v p-p . features 1.8v or 2.5v single-supply operation low power consumption (5.8mw quiescent, 11.7mw average) video load detection directdrive sets video output black level near ground dual spst analog switches transparent input sync-tip clamp i 2 c control applications mobile phones portable media players (pmp) MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ________________________________________________________________ maxim integrated products 1 block diagram ordering information part pin-package pkg code top mark MAX9507ate+ 16 tqfn-ep* t1633+4 afh 19-1028; rev 0; 11/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. note: this device is specified over the -40? to +125? operat- ing temperature range. + denotes lead-free package. * ep = exposed pad. evaluation kit available 0v 2v p-p video MAX9507 a v = 8v/v linear regulator charge pump load detect i 2 c transparent clamp out com1 com2 in lcf no1 no2 250mv p-p video lpf
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +1.8v, gnd = 0v, out has r l = 150 connected to gnd, transparent sync-tip clamp enabled, c 1 = c 2 = 1?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages with respect to gnd.) v dd ...........................................................................-0.3v to +3v cpgnd..................................................................-0.1v to +0.1v in ................................................................-0.3v to (v dd + 0.3v) out, no_, com_ .................(the greater of v ss and -1v) to (v dd + 0.3v) sda, scl, dev_addr, lcf ....................................-0.3v to +4v c1p.............................................................-0.3v to (v dd + 0.3v) c1n .............................................................(v ss - 0.3v) to +0.3v v ss ............................................................................-3v to +0.3v duration of out short circuit to v dd , gnd, and v ss .............................................continuous continuous current in, sda, scl, dev_addr, lcf ....................................?0ma no_, com_ .................................................................?00ma continuous power dissipation (t a = +70?) 16-pin tqfn (derate 15.6mw/? above +70?) ........1250mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply voltage range v dd guaranteed by psrr 1.700 2.625 v filter enabled 3.1 5.4 supply current i dd no load, full operation mode filter disabled 2.9 5.1 ma sleep-mode supply current no load 3 a shutdown supply current i shdn 0.2 10 ? shutdown mode 0.2 switch-only supply current charge-pump-only mode 520 ? output load detect threshold r l to gnd, v sync-tip < 13mv 200 dc-coupled input 1.7v v dd 2.625v 0 262.5 input voltage range guaranteed by output- voltage swing 2.375v v dd 2.625v 0 325 mv input current i b in = 130mv 2 3.2 ? input resistance r in 10mv in 250mv 280 k output level in = 80mv -75 +5 +75 mv ac-coupled input sync-tip clamp level v clp c in = 0.1? -8 0 +11 mv 1.7v v dd 2.625v 252.5 input-voltage swing guaranteed by output- voltage swing 2.375v v dd 2.625v 325 mv p-p sync crush percentage reduction in sync pulse at output, r source = 37.5 , c in = 0.1? 1.6 % input clamping current in = 130mv 2 3.2 ? line-time distortion c in = 0.1? 0.2 % minimum input source resistance 25 output level in = 80mv -75 +5 +75 mv
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dc characteristics dc voltage gain a v guaranteed by output-voltage swing (note 2) 7.84 8 8.16 v/v 0v v in 262.5mv, dc-coupled input 2.058 2.1 2.142 1.7v v dd 2.625v 0v v in 252.5mv p-p , ac-coupled input 1.979 2.02 2.061 output-voltage swing 2.375v v dd 2.625v, 0v v in 325mv 2.548 2.6 2.652 v p-p power-supply rejection ratio psrr 1.7v v dd 2.625v, measured between 75 load resistors 46 60 db shutdown input resistance 0v in v dd 2.8 m output resistance r out out = 0v, -5ma i load +5ma 0.1 shutdown output resistance 0v out v dd 32 m shutdown out leakage current 1a sourcing 82 output short-circuit current sinking 32 ma ac characteristics (filter + 1db passband 7.5 mhz f = 5.5mhz 0 f = 9.3mhz -3 standard-definition reconstruction filter out = 2v p-p , reference frequency is 100khz f = 27mhz -49 db f = 3.58mhz 0.63 differential gain dg f = 4.43mhz 0.93 % f = 3.58mhz 0.50 differential phase dp f = 4.43mhz 0.63 degrees 2t pulse-to-bar k rating 2t = 200ns, bar time is 18?, the beginning 2.5% and the ending 2.5% of the bar time is ignored 0.1 k% 2t pulse response 2t = 200ns 0.3 k% 2t bar response 2t = 200ns, bar time is 18?, the beginning 2.5% and the ending 2.5% of the bar time is ignored 0.2 k% nonlinearity 5-step staircase 0.1 % group-delay distortion 100khz f 5mhz, out = 2v p-p 21 ns peak signal to rms noise 100khz f 5mhz 65 db power-supply rejection ratio psrr f = 100khz, 100mv p-p 47 db output impedance f = 5mhz, in = 80mv 7.5 shutdown out-to-in isolation f < 5.5mhz 102 db shutdown in-to-out isolation f < 5.5mhz 98 db electrical characteristics (continued) (v dd = +1.8v, gnd = 0v, out has r l = 150 connected to gnd, transparent sync-tip clamp enabled, c 1 = c 2 = 1?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1)
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +1.8v, gnd = 0v, out has r l = 150 connected to gnd, transparent sync-tip clamp enabled, c 1 = c 2 = 1?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units ac characteristics (filter small-signal -3db bandwidth out = 100mv p-p 40.7 mhz large-signal -3db bandwidth out = 2v p-p 9.8 mhz small-signal 1db flatness out = 100mv p-p 32.8 mhz large-signal 1db flatness out = 2v p-p 7.2 mhz slew rate out = 2v step 35 v/? settling time to 0.1% out = 2v step 230 ns f = 3.58mhz 0.63 differential gain dg f = 4.43mhz 0.94 % f = 3.58mhz 0.50 differential phase dp f = 4.43mhz 0.64 degrees 2t pulse-to-bar k rating 2t = 200ns, bar time is 18?, the beginning 2.5% and the ending 2.5% of the bar time is ignored 0.1 k% 2t pulse response 2t = 200ns 0.2 k% 2t bar response 2t = 200ns, bar time is 18?, the beginning 2.5% and the ending 2.5% of the bar time is ignored 0.2 k% nonlinearity 5-step staircase 0.1 % group-delay distortion 100khz f 5mhz, out = 2v p-p 15 ns peak signal to rms noise 100khz f 5mhz 69 db power-supply rejection ratio psrr f = 100khz, 100mv p-p 42 db output impedance f = 5mhz, in = 80mv 7.5 shutdown out-to-in isolation f < 5.5mhz 102 db shutdown in-to-out isolation f < 5.5mhz 98 db charge pump switching frequency 325 625 1150 khz analog switches normal range 1.2 2.2 on-resistance (note 3) r on i com_ = 10ma, v no_ = 0v extended range 1.2 2.2 normal range, v no_ = 0v, 1v, v dd 2.3 on-resistance flatness (notes 3, 4) r flat ( on ) i com_ = 10ma extended range, v no_ = -0.9v, 0v, +1.2v, v dd 0.3 1.1 no_ off-leakage current normal range i no_ ( off ) n v dd = 2.625v, v com_ = 0.3v, 2.3v; v no_ = 2.3v, 0.3v; t a = +25? (notes 3, 5) -100 +100 na com_ on-leakage current normal range i com_ ( on ) n v d d = 2.625v , v n o_ = hi g h- z , v c om _ = 0.3v , 2.3v ; t a = + 25 c ( n otes 3, 5) -100 +100 na no_ off-leakage current, extended range i no_ ( off ) e v d d = 2.625v , v c om _ = - 0.6v , + 2.3v ; v n o_ = + 2.3v , - 0.6v ; t a = + 25 c ( n otes 3, 5) -100 +100 na
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +1.8v, gnd = 0v, out has r l = 150 connected to gnd, transparent sync-tip clamp enabled, c 1 = c 2 = 1?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units com_ on-leakage current, extended range i com_ ( on ) e v d d = 2.625v , v n o_ = hi g h- z , v c om _ = - 0.6v , + 2.3v ; t a = + 25c ( n otes 3, 5) -100 +100 na turn-on time t on v no_ = 0.9v, r l = 300 , c l = 35pf, figure 1 (note 6) 310 ns turn-off time t off v no_ = 0.9v, r l = 300 , c l = 35pf, figure 1 (note 6) 372 ns charge injection q v gen = 0.9v, r gen = 0 , c l = 1nf, figure 2 60 pc f = 10mhz 49 off-isolation v iso v no_ = 1v p-p , r l = 50 , c l = 5pf, figure 1 f = 1mhz 69 db on-channel -3db bandwidth bw v no_ = 0dbm, r source = 50 , r l = 50 , c l = 5pf, figure 1 280 mhz total harmonic distortion thd v com_ = 1v p-p , r l = 600 0.037 % charge-pump noise extended range, r l = 50 1.2 mv p-p no_ off-capacitance c off f = 1mhz 21 pf switch on-capacitance c on f = 1mhz 53 pf crosstalk f = 10mhz -71 switch to switch switch 1, 2 closed; v no_ = 1v p-p , r l = 50 , c l = 5pf, figure 1 f = 1mhz -88 db f = 10mhz -44 no_ to out switch 1, 2 open; video circuitry enabled, v no_ = 1v p-p f = 1mhz -78 db out to no_ switch 1, 2 closed; video circuitry enabled, f = 20khz, out = 2v p-p , r l = 50 , c l = 5pf -94 db in to com_ s w i tch 1, 2 cl osed ; vi d eo ci r cui tr y d i sab l ed , f = 20khz, in = 0.25v p-p , r l = 600 -89 db out to com_ switch 1, 2 closed; video circuitry enabled, f = 20khz, out = 2v p-p , r l = 50 , c l = 5pf -94 db cmos digital inputs (sda, scl, dev_addr) input low voltage v il 0.3 x v dd v input high voltage v ih 0.7 x v dd v input hysteresis 275 mv input leakage current i il , i ih -10 +10 ? input capacitance c in 15 pf
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units digital outputs (sda, lcf ) v dd > 2v 0.4 output low voltage v ol i ol = 3ma v dd < 2v 0.2 x v dd v output high leakage current i oh v out = v dd 1a serial interface timing (figure 3) serial clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd,sta 0.6 ? scl pulse-width low t low 1.3 ? scl pulse-width high t high 0.6 ? setup time for a repeated start condition t su,sta 0.6 ? data hold time t hd,dat 0 900 ns data setup time t su,dat 100 ns bus capacitance c b 400 pf sda and scl receiving rise time t r (note 7) 20 + 0.1c b 300 ns sda and scl receiving fall time t f (note 7) 20 + 0.1c b 300 ns v dd = 1.7v 20 + 0.1c b 250 sda transmitting fall time t f (note 7) v dd = 2.625v 0 250 ns setup time for stop condition t su,sto 0.6 ? pulse width of suppressed spike t sp 050ns note 1: all devices are 100% production tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: voltage gain (a v ) is a two-point measurement in which the output-voltage swing is divided by the input-voltage swing. note 3: normal range: charge pump disabled. extended range: charge pump enabled. in extended range mode, the switch input can swing from -0.9v to v dd . note 4: flatness is defined as the difference between the maximum and minimum values of on-resistance as measured at the speci- fied voltages. note 5: not production tested, guaranteed by design. note 6: t on and t off are measured from the end of the writing of register 0x00 until com reaches 90% of the output voltage. see figure 1. note 7: c b is in picofarads. electrical characteristics (continued) (v dd = +1.8v, gnd = 0v, out has r l = 150 connected to gnd, transparent sync-tip clamp enabled, c 1 = c 2 = 1?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1)
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches _______________________________________________________________________________________ 7 test circuits/timing diagrams no_ com_ c l r l sda write register 00h t on t off write register 00h 50% 90% 90% 0v v com_ gnd sda scl i 2 c v dd v dd v no_ v com_ MAX9507 figure 1. analog switch test circuit no_ com_ v gen r gen c l v com_ v com_ q = c l x v com_ on off off switch state gnd sda scl i 2 c v dd v com_ v dd MAX9507 figure 2. analog switch charge injection scl sda start condition stop condition repeated start condition start condition t hd,sta t su,sta t hd,sta t sp t buf t su,sto t low t su,dat t hd,dat t high t r t f figure 3. i 2 c serial-interface timing diagram
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 8 _______________________________________________________________________________________ typical operating characteristics (v dd = +1.8v, gnd = 0v, mode 2 (table 6), video output has r l = 150 connected to gnd, video filter enabled, t a = +25?, unless otherwise noted.) small-signal gain vs. frequency MAX9507 toc01 frequency (hz) gain (db) 100m 10m 1m -80 -60 -40 -20 0 20 -100 100k 1g flten = 0 flten = 1 v out = 100mv p-p small-signal gain flatness vs. frequency MAX9507 toc02 frequency (hz) gain (db) 10m 1m -2 -1 0 1 2 -3 100k 100m flten = 0 flten = 1 v out = 100mv p-p large-signal gain vs. frequency MAX9507 toc03 frequency (hz) gain (db) 100m 10m 1m -80 -60 -40 -20 0 20 -100 100k 1g flten = 0 flten = 1 v out = 2v p-p large-signal gain flatness vs. frequency MAX9507 toc04 frequency (hz) gain (db) 10m 1m -2 1 0 -1 2 -3 100k 100m v out = 2v p-p flten = 1 flten = 0 large-signal group delay vs. frequency MAX9507 toc05 frequency (hz) delay (ns) 100m 10m 1m 10 20 30 40 50 60 70 80 90 100 0 100k 1g flten = 0 flten = 1 v out = 2v p-p small-signal group delay vs. frequency MAX9507 toc06 frequency (hz) delay (ns) 100m 10m 1m 10 20 30 40 50 60 70 80 90 100 0 100k 1g flten = 0 flten = 1 v out = 100mv p-p power-supply rejection ratio vs. frequency MAX9507 toc07 frequency (hz) gain (db) 10m 1m 100k -80 -60 -40 -20 0 20 -100 10k 100m flten = 0 flten = 1 quiescent supply current vs. temperature MAX9507 toc08 temperature ( c) quiescent supply current (ma) 100 75 50 25 0 -25 3.0 2.5 3.5 4.0 2.0 -50 125 flten = 1 flten = 0 voltage gain vs. temperature MAX9507 toc09 temperature ( c) voltage gain (v/v) 100 75 50 25 0 -25 8.05 7.95 7.90 7.85 8.00 8.10 8.15 8.20 7.80 -50 125
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches _______________________________________________________________________________________ 9 output voltage vs. input voltage MAX9507 toc10 input voltage (mv) output voltage (v) 350 300 250 200 150 100 50 0 -50 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -1.5 -100 400 differential gain and phase (flten = 1) MAX9507 toc11 differential gain (%) differential phase (deg) 0 0.4 0.8 1.2 -0.4 -0.8 0 0.4 0.8 -0.4 -0.8 1.2 200 168 dc input level (mv) dc input level (mv) 136 104 71 232 200 168 136 104 71 232 frequency = 3.58mhz v in = 71mv p-p differential gain and phase (flten = 1) MAX9507 toc12 differential gain (%) differential phase (deg) 0 0.4 0.8 1.2 -0.4 -0.8 0 0.4 0.8 -0.4 -0.8 1.2 200 168 dc input level (mv) dc input level (mv) 136 104 71 232 200 168 136 104 71 232 frequency = 4.43mhz v in = 71mv p-p differential gain and phase (flten = 0) MAX9507 toc13 differential gain (%) differential phase (deg) 0 0.4 0.8 1.2 -0.4 -0.8 0 0.4 0.8 -0.4 -0.8 1.2 200 168 dc input level (mv) dc input level (mv) 136 104 71 232 200 168 136 104 71 232 frequency = 3.58mhz v in = 71mv p-p differential gain and phase (flten = 0) MAX9507 toc14 differential gain (%) differential phase (deg) 0 0.4 0.8 1.2 -0.4 -0.8 0 0.4 0.8 -0.4 -0.8 1.2 200 168 dc input level (mv) dc input level (mv) 136 104 71 232 200 168 136 104 71 232 frequency = 4.43mhz v in = 71mv p-p 2t response MAX9507 toc15 400ns/div in 100mv/div 0v out 500mv/div 0v 12.5t response MAX9507 toc16 400ns/div in 100mv/div 0v out 500mv/div 0v ntc-7 response MAX9507 toc17 10 s/div in 100mv/div 0v out 500mv/div 0v pal multiburst MAX9507 toc18 10 s/div in 100mv/div 0v out 1v/div 0v typical operating characteristics (continued) (v dd = +1.8v, gnd = 0v, mode 2 (table 6), video output has r l = 150 connected to gnd, video filter enabled, t a = +25?, unless otherwise noted.)
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 10 ______________________________________________________________________________________ pal color bars MAX9507 toc19 10 s/div in 100mv/div 0v out 1v/div 0v field square-wave response (ac-coupled input) MAX9507 toc20 10 s/div in 100mv/div 0v out 500mv/div 0v small-signal pulse response (flten = 0) MAX9507 toc21 100ns/div input (6.25mv/div) output (50mv/div) large-signal pulse response (flten = 0) MAX9507 toc22 100ns/div input (125mv/div) output (1v/div) on-resistance vs. com_ voltage (normal range) MAX9507 toc23 com_ voltage (v) on-resistance ( ) 2.5 2.0 0.5 1.0 1.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0 3.0 v dd = 2.5v v dd = 1.8v on-resistance vs. com_ voltage (extended range) MAX9507 toc24 com_ voltage (v) on-resistance ( ) 2.5 2.0 -0.5 0 0.5 1.0 1.5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 -1.0 3.0 v dd = 2.5v v dd = 1.8v on-resistance vs. com_ voltage (normal range) MAX9507 toc25 com_ voltage (v) on-resistance ( ) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1 2 3 4 5 6 7 0 02.0 t a = -40 c t a = +25 c t a = +125 c on-resistance vs. com_ voltage (extended range) MAX9507 toc26 com_ voltage (v) on-resistance ( ) 1.5 1.0 0.5 0 -0.5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 -1.0 2.0 t a = -40 c t a = +25 c t a = +125 c analog switch leakage current vs. temperature (normal range) MAX9507 toc27 temperature ( c) leakage current (na) 100 75 50 25 0 -25 0 1 2 3 4 5 6 -1 -50 125 com on com off v dd = 2.625v typical operating characteristics (continued) (v dd = +1.8v, gnd = 0v, mode 2 (table 6), video output has r l = 150 connected to gnd, video filter enabled, t a = +25?, unless otherwise noted.)
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 11 analog switch leakage current vs. temperature (extended range) MAX9507 toc28 temperature ( c) leakage current (na) 100 75 50 25 0 -25 0 1 2 3 4 5 6 -1 -50 125 com on com off v dd = 2.625v switch charge injection vs. voltage MAX9507 toc29 switch input voltage (v) switch charge injection (pc) 1.5 1.0 0 0.5 -0.5 100 200 300 400 500 0 -1.0 2.0 c load = 1nf open = 1 open = 0 switch-only supply current vs. temperature (normal range) MAX9507 toc30 temperature ( c) supply current (na) 100 75 50 25 0 -25 50 100 150 200 250 300 0 -50 125 spen = 0 cpen = 0 switch frequency response MAX9507 toc31 frequency (hz) gain (db) 100m 10m 1m -25 -20 -15 -10 -5 0 5 -30 100k 1g r l = 50 c l = 5pf switch off-isolation vs. frequency MAX9507 toc32 frequency (hz) gain (db) 100m 10m 1m -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 100k 1g switch-to-switch crosstalk vs. frequency MAX9507 toc33 frequency (hz) isolation (db) 10m 1m -100 -80 -60 -40 -20 0 -120 100k 100m total harmonic distortion plus noise vs. frequency MAX9507 toc34 frequency (hz) thd+n (%) 10k 1k 100 10 100k 0.1 0.01 v in = 2v p-p r load = 600 typical operating characteristics (continued) (v dd = +1.8v, gnd = 0v, mode 2 (table 6), video output has r l = 150 connected to gnd, video filter enabled, t a = +25?, unless otherwise noted.)
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 12 ______________________________________________________________________________________ pin description pin name function 1 in video input 2 sda i 2 c-compatible serial-data input/output 3 scl i 2 c-compatible serial-clock input 4 dev_addr i 2 c device address input. connect dev_addr to gnd, v dd , scl, or sda. see table 4. 5v dd positive power supply. bypass with a 0.1? capacitor to gnd. 6 c1p charge-pump flying capacitor positive terminal. connect a 1? capacitor from c1p to c1n. 7 cpgnd charge-pump ground 8 c1n charge-pump flying capacitor negative terminal. connect a 1? capacitor from c1p to c1n. 9v ss charge-pump negative power supply. bypass with a 1? capacitor to gnd. 10 out video output 11 gnd ground 12 lcf load change flag. open-drain, active-low signal indicates when a video load change occurs. 13 no1 normally open terminal 1 14 com1 common terminal 1 15 com2 common terminal 2 16 no2 normally open terminal 2 ep exposed pad. ep is internally connected to gnd. connect ep to gnd. detailed description the MAX9507 represents maxim? second-generation of directdrive video amplifiers that meet the require- ments of current and future portable equipment: 1.8v operation: eliminate the need for 3.3v supply in favor of lower supply voltages. lower power consumption: the MAX9507 reduces average power consumption by up to 75% com- pared to the 3.3v first generation (max9503/ max9505). internal fixed gain of 8: as the supply voltages drop for system chips on deep submicron processes, the video dac can no longer create a 1v p-p signal at its output, and the gain of 2 found in the previous gen- eration of video filter amplifiers is not enough. load reporting: the MAX9507 senses the presence of a video load. for portable devices, a video load is not connected most of the time, and turning off the video encoder saves power. another benefit of load reporting is a simpler user interface, eliminating the need to browse through menus to activate the video output. instead, the equipment will automatically enable this feature. dual spst analog switches: the two analog switch- es are ideal for routing additional audio, video, or digital signals. directdrive technology is necessary for a voltage-mode amplifier to output a 2v p-p video signal from a 1.8v supply. the integrated inverting charge pump creates a negative supply that increases the output range and gives the video amplifier enough headroom to drive a 2v p-p video signal into a 150 load. directdrive background integrated video filter amplifier circuits operate from a single supply. the positive power supply usually cre- ates video output signals that are level-shifted above ground to keep the signal within the linear range of the output amplifier. for applications where the positive dc level is not acceptable, a series capacitor can be inserted in the output connection in an attempt to elimi- nate the positive dc level shift. the series capacitor cannot truly level shift a video signal because the aver- age level of the video varies with picture content. the series capacitor biases the video output signal around ground, but the actual level of the video signal can vary significantly depending upon the rc time constant and the picture content.
the series capacitor creates a highpass filter. since the lowest frequency in video is the frame rate, which can be between 24hz and 30hz, the pole of the highpass filter should ideally be an order of magnitude lower in fre- quency than the frame rate. therefore, the series capaci- tor must be very large, typically from 220? to 3000?. for space-constrained equipment, the series capacitor is unacceptable. changing from a single series capaci- tor to a sag network that requires two smaller capacitors can only reduce space and cost slightly. the series capacitor in the usual output connection also prevents damage to the output amplifier if the con- nector is shorted to a supply or to ground. while the output connection of the MAX9507 does not have a series capacitor, the MAX9507 will not be damaged if the connector is shorted to a supply or to ground (see the short-circuit protection section). video amplifier if the full-scale video signal from a video dac is 250mv, the black level of the video signal created by the video dac is around 75mv. the MAX9507 shifts the black level to near ground at the output so that the active video is above ground and the sync is below ground. the amplifier needs a negative supply for its output stage to remain in its linear region when driving sync below ground. the MAX9507 has an integrated charge pump and lin- ear regulator to create a low-noise negative supply from the positive supply voltage. the charge pump inverts the positive supply to create a raw negative volt- age that is then fed into the linear regulator filtering out the charge-pump noise. comparison between directdrive output and ac-coupled output the actual level of the video signal varies less with a directdrive output than an ac-coupled output. the average video signal level can change greatly depend- ing upon the picture content. with an ac-coupled out- put, the average level will change according to the time constant formed by the series capacitor and series resistance (usually 150 ). for example, figure 4 shows an ac-coupled video signal alternating between a completely black screen and a completely white screen. notice the excursion of the video signal as the screen changes. with the directdrive amplifier, the black level is held at ground. the video signal is constrained between -0.3v to +0.7v. figure 5 shows the video signal from a directdrive amplifier with the same input signal as the ac-coupled system. video reconstruction filter the MAX9507 includes an internal five-pole, butterworth lowpass filter to condition the video signal. the reconstruction filter smoothes the steps and reduces the spikes created whenever the dac output changes value. in the frequency domain, the steps and spikes cause images of the video signal to appear at multiples of the sampling clock frequency. the recon- struction filter typically has ?db passband flatness of 7.3mhz and 48db attenuation at 27mhz. MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 13 input output 2ms/div input output 2ms/div 0v 0v figure 4. ac-coupled output figure 5. directdrive output
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 14 ______________________________________________________________________________________ transparent sync-tip clamp the MAX9507 contains an integrated, transparent sync-tip clamp. when using a dc-coupled input, the sync-tip clamp does not affect the input signal, as long as it remains above ground. when using an ac-cou- pled input, the sync-tip clamp automatically clamps the input signal to ground, preventing it from going lower. a small current of 2? pulls down on the input to prevent an ac-coupled signal from drifting outside the input range of the device. using an ac-coupled input results in some additional variation of the black level at the output. applying a voltage above ground to the input pin of the device always produces the same output voltage, regardless of whether the input is dc- or ac-coupled. however, since the sync-tip clamp level (v clp ) can vary over a small range, the video black level at the output of the device when using an ac-coupled input can vary by an additional amount equal to the v clp multiplied by the dc voltage gain (a v ). dual spst analog switches the MAX9507 has dual spst analog switches for rout- ing additional audio, video, digital, and other signals. the switches are selected through the i 2 c interface. sw1en (register 0x00, bit b6) and sw2en (register 0x00, bit b7) control the analog switches. see the i 2 c registers and bit descriptions section. the dual analog switches operate in either normal or extended range. in normal range, the part is in shutdown and the analog switches can handle signals between gnd and v dd . in extended range, the charge pump and linear regulator are on and the analog switches can handle signals between -0.9v and v dd . short-circuit protection the MAX9507 typical operating circuit includes a 75 back-termination resistor that limits short-circuit current if an external short is applied to the video output. the MAX9507 also features internal output short-circuit pro- tection to prevent device damage in prototyping and applications where the amplifier output can be directly shorted. powering on/off the MAX9507 the MAX9507 powers on in a low-power shutdown mode with the analog switches open and the video sig- nal path, charge pump, and load detection circuitry disabled. it is good practice to configure the operating mode of the signal path before enabling it. this may include selecting the sync-tip clamp and video filter. setting cpen = 1 (register 0x00, bit b0) enables the charge pump. the charge pump must be fully opera- tional before the signal path will be functional. setting spen = 1 (register 0x00, bit b1) enables the signal path. both spen and cpen may be set at the same time and internal control circuitry will monitor the charge pump and enable the signal path at the appro- priate time. the analog switches can be turned on or off at any time, regardless of the state of the charge pump or sig- nal path. however, the signal range is limited from gnd to v dd when the charge pump is disabled. the MAX9507 can be placed in a low-power shutdown mode by setting spen = 0 and cpen = 0. video load detection circuitry the MAX9507 contains video load detection circuitry at the video output, enabling efficient power consumption based on the actual presence of a video load. setting the automatic signal path enable bit, aspen = 1 (regis- ter 0x01, bit b1) or the automatic charge-pump enable bit, acpen = 1 (register 0x01, bit b0) enables the load detection feature. the load bit (register 0x01, bit b7) indicates the load status. to enable complete, automatic control of the part, set aspen = acpen = 1 and spen = cpen = 0. in this state, when an output load is connected to the amplifi- er, the signal path and charge pump fully turn on and stay on until the output load is disconnected. if an out- put load is not connected to the amplifier, then the sig- nal path and charge pump remain in a low-power sleep mode while continuing to check if a load is connected. setting spen = 1 or cpen = 1 overrides the corre- sponding aspen or acpen bits, enabling the block regardless of the detected video load status. the load bit indicates the latest video load status. all changes to the video load status are debounced typi- cally 128ms to eliminate false load-detect events. setting the load change flag enable bit, lcfen = 1 (reg- ister 0x01, bit b3), and enabling the load detection fea- ture (aspen = 1 or acpen = 1) enables the open-drain lcf output. lcf asserts low whenever the load bit changes state. it remains low until the load bit (register 0x01) is read. lcf can be used as an interrupt to notify the system that the load status has changed.
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 15 sleep mode if a video load is not connected to the amplifier, the MAX9507 remains in a low-power sleep mode. the load-sense circuitry checks for a load eight times per second by connecting an internal 7.5k pullup resistor to the output for 1ms. if the output is pulled up, no load is present. if the output stays low, a load is connected, and the automatic control circuitry enables the appro- priate blocks. when the amplifier is on, it continually checks if the load has been disconnected by detecting if the amplifier is sinking current during a horizontal line time. therefore, a black-burst signal (or input signal < 13mv) is required to maintain the detected load sta- tus. if the load is disconnected, the device returns to the low-power sleep mode. common modes of operation x = don? care. no. mode aspen acpen spen cpen 1 shutdown mode. switches in normal range. load-detect function disabled. 0000 2 full operation mode. video, charge pump, and regulator on. switches in extended range. xx11 3 charge-pump-only mode. charge pump and regulator on, video off. switches in extended range. xx01 4 sleep mode. video, charge pump, and regulator automatic. switches in extended range only when the charge pump is on. load-detect function enabled. 1100 5 charge pump and regulator on, video automatic. switches in extended range. load-detect function enabled. 1001 i 2 c registers and bit descriptions table 1. register map register address register b7 b6 b5 b4 b3 b2 b1 b0 power-on reset state 0x00 configuration sw2en sw1en 0 sten flten 0 spen cpen 0x00 0x01 video load detect load 0 0 0 lcfen 0 aspen acpen 0x00
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 16 ______________________________________________________________________________________ i 2 c serial interface the MAX9507 features an i 2 c/smbus-compatible, 2- wire serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facilitate communication between the MAX9507 and the master at clock rates up to 400khz. figure 3 shows the 2-wire inter- face timing diagram. the master generates scl and initi- ates data transfer on the bus. a master device writes data to the MAX9507 by transmitting a start (s) condition, the proper slave address with the r/ w bit set to 0, fol- lowed by the register address and then the data word. each transmit sequence is framed by a start (s) and a stop (p) condition. each word transmitted to the MAX9507 is 8 bits long and is followed by an acknowl- edge clock pulse. a master reads from the MAX9507 by transmitting the slave address with the r/ w bit set to 0, the register address of the register to be read, a repeat- ed start (sr) condition, the slave address with the r/ w bit set to 1, followed by a series of scl pulses. the MAX9507 transmits data on sda in sync with the master- generated scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, an acknowledge or a not acknowledge, and a stop condition. sda oper- ates as both an input and an open-drain output. a pullup resistor, typically greater than 500 , is required on the sda bus. scl operates as only an input. a pullup resis- tor, typically greater than 500 , is required on scl if there are multiple masters on the bus, or if the master in a single-master system has an open-drain scl output. table 2. configuration register (0x00) bit name function b7 sw2en 1 = analog switch 2 closed. 0 = analog switch 2 open. b6 sw1en 1 = analog switch 1 closed. 0 = analog switch 1 open. b4 sten 1 = transparent sync-tip clamp enabled, the input can be dc- or ac-coupled. 0 = transparent sync-tip clamp disabled, the input must be dc-coupled. b3 flten 1 = video filter enabled. 0 = video filter disabled (bypassed). b1 spen 1 = signal path enabled* (spen overrides the aspen setting). 0 = signal path disabled. b0 cpen 1 = charge pump enabled (cpen overrides the acpen setting). 0 = charge pump disabled. * internal control circuitry prevents the signal path from turning on until the charge pump has been enabled and has settled. table 3. video load-detect register (0x01) bit name function b7 load* 1 = load detected. 0 = no load detected. b3 lcfen 1 = changes to the video load will trigger lcf to pull low. 0 = changes to the video load are not reported. b1 aspen 1 = enable automatic control of the video signal path**. 0 = disable automatic control of the video signal path. b0 acpen 1 = enable automatic control of the charge pump***. 0 = disable automatic control of the charge pump. * read-only bit indicating the load status when the video load-detect circuitry is enabled (aspen = 1 or acpen = 1). when lcfen = 1, reading this bit will clear the lcf flag. ** if spen = 0, then the signal path will be automatically enabled when a video load is detected and the charge pump has been enabled and has settled. *** if cpen = 0, then the charge pump will be automatically enabled when a video load is detected. smbus is a trademark of intel corp.
series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX9507 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). sda and scl idle high when the i 2 c bus is not busy. start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start con- dition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 6). a start condition from the master signals the beginning of a transmission to the MAX9507. the master terminates transmission, and frees the bus, by issuing a stop con- dition. the bus remains active if a repeated start condition is generated instead of a stop condition. early stop conditions the MAX9507 recognizes a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the slave address is defined as the 7 most significant bits (msbs) followed by the read/write (r/ w ) bit. set the r/ w bit to 1 to configure the MAX9507 to read mode. set the r/ w bit to 0 to configure the MAX9507 to write mode. the slave address is always the first byte of information sent to the MAX9507 after a start or a repeated start condition. the MAX9507 slave address is configurable with dev_addr. table 4 shows the possible slave addresses for the MAX9507. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the MAX9507 uses to handshake receipt of each byte of data when in write mode (see figure 7). the MAX9507 pulls down sda during the entire master-generated ninth clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master may retry communication. the master pulls down sda during the ninth clock cycle to acknowledge receipt of data when the MAX9507 is in read mode. an acknowl- edge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the MAX9507, followed by a stop condition. MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 17 dev_addr b7 b6 b5 b4 b3 b2 b1 b0 write address (hex) read address (hex) gnd 1001100r/ w 0x98 0x99 v dd 1001101r/ w 0x9a 0x9b scl 1001110r/ w 0x9c 0x9d sda 1001111r/ w 0x9e 0x9f scl sda ssrp figure 6. start, stop, and repeated start conditions 1 scl start condition sda 289 clock pulse for acknowledgment acknowledge not acknowledge figure 7. acknowledge table 4. slave address
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 18 ______________________________________________________________________________________ write data format a write to the MAX9507 consists of transmitting a start condition, the slave address with the r/ w bit set to 0, one data byte to configure the internal register address pointer, one or more data bytes, and a stop condition. figure 8 illustrates the proper frame format for writing one byte of data to the MAX9507. figure 9 illustrates the frame format for writing n-bytes of data to the MAX9507. the slave address with the r/ w bit set to 0 indicates that the master intends to write data to the MAX9507. the MAX9507 acknowledges receipt of the address byte during the master-generated ninth scl pulse. the second byte transmitted from the master config- ures the MAX9507? internal register address pointer. the pointer tells the MAX9507 where to write the next byte of data. an acknowledge pulse is sent by the MAX9507 upon receipt of the address pointer data. the third byte sent to the MAX9507 contains the data that will be written to the chosen register. an acknowl- edge pulse from the MAX9507 signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this autoincrement feature allows a master to write to sequential register address locations within one contin- uous frame. the master signals the end of transmission by issuing a stop condition. read data format the master presets the address pointer by first sending the MAX9507? slave address with the r/ w bit set to 0 followed by the register address after a start condi- tion. the MAX9507 acknowledges receipt of its slave address and the register address by pulling sda low during the ninth scl clock pulse. a repeated start condition is then sent followed by the slave address with the r/ w bit set to 1. the MAX9507 transmits the contents of the specified register. transmitted data is valid on the rising edge of the master-generated serial clock (scl). the address pointer autoincrements after each read data byte. this autoincrement feature allows all registers to be read sequentially within one continu- ous frame. a stop condition can be issued after any number of read data bytes. if a stop condition is issued followed by another read operation, the first a 0 slave address register address data byte acknowledge from MAX9507 r/w 1 byte autoincrement internal register address pointer acknowledge from MAX9507 acknowledge from MAX9507 b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 8. writing a byte of data to the MAX9507 1 byte autoincrement internal register address pointer acknowledge from MAX9507 acknowledge from MAX9507 b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from MAX9507 r/w s a 1 byte acknowledge from MAX9507 b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n figure 9. writing n-bytes of data to the MAX9507
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 19 data byte to be read will be from the register address location set by the previous transaction and not 0x00, and subsequent reads will autoincrement the address pointer until the next stop condition. attempting to read from register addresses higher than 0x01 results in repeated reads from a dummy register containing 0xff data. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condition. figures 10 and 11 illustrate the frame format for reading data from the MAX9507. applications information power consumption the quiescent power consumption and average power consumption of the MAX9507 is remarkably low because of 1.8v operation and directdrive technology. quiescent power consumption is defined when the MAX9507 is operating without load. in this case, the MAX9507 consumes about 5.8mw. average power consumption, which is defined when the MAX9507 dri- ves a 150 load to ground with a 50% flat field, is about 11.7mw. table 5 shows the power consumption with different video signals. the supply voltage is 1.8v and out drives a 150 load to ground. notice that the two extremes in power consumption occur with a video signal that is all black and a video signal that is all white. the power consumption with 75% color bars and 50% flat field lies in between the extremes. acknowledge from MAX9507 1 byte autoincrement internal register address pointer acknowledge from MAX9507 a a a 0 acknowledge from MAX9507 r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 11. reading n-bytes of indexed data from the MAX9507 acknowledge from MAX9507 1 byte autoincrement internal register address pointer acknowledge from MAX9507 not acknowledge from master a a p a 0 acknowledge from MAX9507 r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 10. reading one indexed byte of data from the MAX9507 video signal MAX9507 power consumption with filter enabled (mw) MAX9507 power consumption with filter disabled (mw) all black screen 6.7 6.2 all white screen 18.2 17.9 75% color bars 11.6 11.0 50% flat field 11.7 11.3 table 5. MAX9507 power consumption with different video signals
MAX9507 interfacing to video dacs that produce video signals larger than 0.25v p-p devices designed to generate 1v p-p video signals at the output of the video dac can still work with the MAX9507. most video dacs source current into a ground-referenced resistor, which converts the current into a voltage. figure 12 shows a video dac that cre- ates a video signal from 0 to 1v across a 150 resistor. the following video filter amplifier has a 2v/v gain so that the output is 2v p-p . the MAX9507 expects input signals that are 0.25v p-p nominally. the same video dac can be made to work with the MAX9507 by scaling down the 150 resistor to a 37.5 resistor, as shown in figure 13. the 37.5 resis- tor is one-quarter the size of the 150 resistor, resulting in a video signal that is one-quarter the amplitude. changing between video output and microphone input on a single connector figure 14 shows how a single pole on a mobile phone jack can be used for transmitting a video signal to a television or receiving the signal from the microphone of a headset. to transmit a video signal, open sw1 and enable the video circuitry. to receive a signal from a microphone, close sw1 and disable the video circuitry. switching between video and digital signals figure 15 shows how the dual spst analog switches and the high-impedance output of the video amplifier enable video transmission, digital transmission, and digital reception all on a single pole of a connector. to transmit a video signal, open sw1 and sw2 and enable the video circuitry. to receive a digital signal, close sw1, open sw2, and disable the video circuitry. to transmit a digital signal, open sw1, close sw2, and disable the video circuitry. selecting between two video sources the analog switches can multiplex between two video sources. for example, a mobile phone might have an application processor with an integrated video encoder and a mobile graphics processor with an integrated video encoder, each creating a composite video signal that is between 0 and 0.25v. figure 16 shows this appli- cation in which the MAX9507 chooses between two inter- nal video sources. the two analog switches can be used as a 2:1 multiplexer to select which video dac output is filtered, amplified, and driven out to the connector. if the analog switches are in extended mode, then they can also be used to select between two external video signals, as shown in figure 17. the external video sig- nals are usually between -2v and +2v. the resistor net- work divides the external signal by a factor of four, thereby reducing the signal to between -0.5v and +0.5v (see the anti-alias filter section for an explanation on why the resistor-divider network is necessary). in extend- ed mode, the analog switch can easily handle this bipo- lar input signal, even if the supply voltage is 1.8v. 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 20 ______________________________________________________________________________________ 150 0 to 1v lpf dac image processor asic 75 2v p-p 2v/v 37.5 0 to 0.25v lpf dac image processor asic MAX9507 75 2v p-p 8v/v figure 12. video dac generates a 1v p-p signal across a 150 resistor connected to ground figure 13. video dac generates a 0.25v p-p signal across a 37.5 resistor connected to ground
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 21 MAX9507 mic amp mic bias load detect i 2 c interface sw1 com1 no1 sw2 com2 no2 scl in 1.8v sda v dd gnd out charge pump linear regulator c1 1 f c2 1 f c3 0.1 f v cc baseband ic a v = 8v/v lpf transparent clamp dc level shift to jack lcf dac video asic 75 v cc v cc cpgnd c1p c1n v ss v dd figure 14. video output configuration
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 22 ______________________________________________________________________________________ MAX9507 load detect i 2 c interface sw1 com1 no1 sw2 com2 no2 scl in 1.8v sda v dd gnd out charge pump linear regulator c1 1 f c2 1 f c3 0.1 f v cc a v = 8v/v lpf v dd transparent clamp dc level shift to jack lcf dac video asic 75 v cc v cc cpgnd c1p c1n v ss baseband ic figure 15. video output configuration
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 23 MAX9507 load detect i 2 c interface sw1 com1 no1 sw2 com2 no2 scl in 1.8v sda v dd gnd out charge pump linear regulator c1 1 f c2 1 f c3 0.1 f v cc a v = 8v/v lpf transparent clamp dc level shift lcf dac mobile gpu dac application processor 75 cpgnd c1p c1n v ss microcontroller v dd figure 16. selecting between two internal video sources
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 24 ______________________________________________________________________________________ MAX9507 load detect i 2 c interface sw1 com1 no1 sw2 com2 no2 scl in 1.8v sda v dd gnd out charge pump linear regulator c1 1 f c2 1 f c3 0.1 f v cc a v = 8v/v lpf transparent clamp dc level shift lcf 75 10 0.1 f cpgnd c1p c1n v ss microcontroller vidin1 56 vidin2 56 v dd 18 18 figure 17. selecting between two external video sources
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 25 anti-alias filter the MAX9507 can also provide anti-alias filtering with a buffer before an analog-to-digital converter (adc), which would be present in an ntsc/pal video decoder, for example. figure 18 shows the application circuit. an external composite video signal is applied to vidin, which is terminated with a total of 74 (56 and 18 resistors) to ground. the signal is attenuated by four, and then ac-coupled to in. the normal 1v p-p video sig- nal must be attenuated because with a 1.8v supply, the MAX9507 can only handle a video signal of approxi- mately 0.25v p-p at in. ac-couple the video signal to in because the dc level of an external video signal is usu- ally not well specified, although it is reasonable to expect that the signal is between -2v and +2v. the 10 series resistor increases the equivalent source resis- tance to about 25 , which is the minimum necessary for a video source to drive the internal sync-tip clamp. for external video signals larger than 1v p-p , then oper- ate the MAX9507 from a 2.5v supply so that in can accommodate a 0.325v p-p video signal, which is equiv- alent to a 1.3v p-p video signal at vidin. MAX9507 load detect i 2 c interface sw1 com1 no1 sw2 com2 no2 scl in 1.8v sda v dd gnd out charge pump linear regulator c1 1 f c2 1 f c3 0.1 f v cc a v = 8v/v lpf transparent clamp dc level shift lcf 75 10 0.1 f cpgnd c1p c1n v ss microcontroller vidin 56 v dd 18 figure 18. MAX9507 used as an anti-alias filter with buffer
MAX9507 power-supply bypassing and ground management the MAX9507 operates from a 1.7v to 2.625v single supply and requires proper layout and bypassing. for the best performance, place the components as close to the device as possible. proper grounding improves performance and prevents any switching noise from coupling into the video signal. bypass the analog supply (v dd ) with a 0.1? capacitor to gnd, placed as close to the device as possible. bypass cpv ss with a 1? capacitor to gnd as close to the device as possible. the total system bypass capac- itance on v dd should be at least 10?, or ten times the capacitance between c1p and c1n. using a digital supply the MAX9507 is designed to operate from noisy digital supplies. the high power-supply rejection ratio (47db at 100khz) allows the MAX9507 to reject the noise from the digital power supplies (see the typical operating characteristics ). if the digital power supply is very noisy and stripes appear on the television screen, increase the supply bypass capacitance. an additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resis- tance (esr) and equivalent series inductance (esl). 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 26 ______________________________________________________________________________________ chip information process: bicmos pin configuration 15 16 14 13 *ep *exposed pad connected to gnd. + 5 6 7 scl dev_addr 8 in out v ss lcf 13 com1 4 12 10 9 com2 no2 c1n cpgnd c1p v dd MAX9507 sda gnd 2 11 no1 thin qfn (3mm x 3mm) top view
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches ______________________________________________________________________________________ 27 functional diagram/typical operating circuit MAX9507 load detect i 2 c interface sw1 com1 no1 sw2 com2 no2 scl in 1.8v sda v dd gnd out charge pump linear regulator c1 1 f c2 1 f c3 0.1 f v cc a v = 8v/v lpf transparent clamp dc level shift to jack lcf dac video asic 75 v cc v cc cpgnd c1p c1n v ss microcontroller v dd
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches 28 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 12x16l qfn thin.eps 0.10 c 0.08 c 0.10 m c a b d d/2 e/2 e a1 a2 a e2 e2/2 l k e (nd - 1) x e (ne - 1) x e d2 d2/2 b l e l c l e c l l c l c package outline 21-0136 2 1 i 8, 12, 16l thin qfn, 3x3x0.8mm marking aaaa
MAX9507 1.8v directdrive video filter amplifier with load detection and dual spst analog switches maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 29 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) exposed pad variations codes pkg. t1233-1 min. 0.95 nom. 1.10 d2 nom. 1.10 max. 1.25 min. 0.95 max. 1.25 e2 12 n k a2 0.25 ne a1 nd 0 0.20 ref - - 3 0.02 3 0.05 l e e 0.45 2.90 b d a 0.20 2.90 0.70 0.50 bsc. 0.55 3.00 0.65 3.10 0.25 3.00 0.75 0.30 3.10 0.80 16 0.20 ref 0.25 - 0 4 0.02 4 - 0.05 0.50 bsc. 0.30 2.90 0.40 3.00 0.20 2.90 0.70 0.25 3.00 0.75 3.10 0.50 0.80 3.10 0.30 pkg ref. min. 12l 3x3 nom. max. nom. 16l 3x3 min. max. 0.35 x 45 pin id jedec weed-1 t1233-3 1.10 1.25 0.95 1.10 0.35 x 45 1.25 weed-1 0.95 t1633f-3 0.65 t1633-4 0.95 0.80 0.95 0.65 0.80 1.10 1.25 0.95 1.10 0.225 x 45 0.95 weed-2 0.35 x 45 1.25 weed-2 t1633-2 0.95 1.10 1.25 0.95 1.10 0.35 x 45 1.25 weed-2 package outline 21-0136 2 2 i 8, 12, 16l thin qfn, 3x3x0.8mm weed-1 1.25 1.10 0.95 0.35 x 45 1.25 1.10 0.95 t1233-4 t1633fh-3 0.65 0.80 0.95 0.225 x 45 0.65 0.80 0.95 weed-2 notes: 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals . 9. drawing conforms to jedec mo220 revision c. 10. marking is for package orientation reference only. 11. number of leads shown are for reference only. 12. warpage not to exceed 0.10mm. 0.25 0.30 0.35 2 0.25 0 0.20 ref - - 0.02 0.05 0.35 8 2 0.55 0.75 2.90 2.90 3.00 3.10 0.65 bsc. 3.00 3.10 8l 3x3 min. 0.70 0.75 0.80 nom. max. tq833-1 1.25 0.25 0.70 0.35 x 45 weec 1.25 0.70 0.25 t1633-5 0.95 1.10 1.25 0.35 x 45 weed-2 0.95 1.10 1.25

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